Stratix® 10 FPGA – IOPLL Dynamic Phase Shift Design Example - This design demonstrates the implementation of the I/O PLL dynamic phase shift directly through the IOPLL Altera® FPGAs IP core without using the IOPLL Reconfig Altera® FPGAs IP core. You can use the dynamic phase shift ports to determine the number of shifts, the direction of the phase shift, and the output clock to be shifted. - 2017-10-27

Version

17.1.0