Stratix® 10 FPGA – IOPLL Advanced Mode Reconfiguration Design Example - In Advanced Mode, the individual I/O PLL setting is reconfigured using the IOPLL Reconfig Altera® FPGAs IP core through the Avalon® interface. This reference design demonstrates the implementation of the Advanced Mode I/O PLL reconfiguration. - 2018-12-26

Version

18.1.0