Stratix® 10 FPGA – H-Tile Multi-Loopback Modes Simulation Design Example - This design example demonstrates how to enable and disable the different loopback modes supported in the Stratix® 10 FPGA H-Tile transceiver physical media access (PMA) in real time using the direct reconfiguration flow. The loopback modes demonstrated in this design include serial loopback and post-CDR reverse serial loopback. The design will also show a link test between two transceiver channels with different loopback modes in a Modelsim* simulation. - 2017-04-10

Version

17.0.0