MAX® 10 FPGA – Software Design Example for Avalon® Streaming (Avalon-ST) Interface Configuration Design Example - In this design, we demonstrate how to configure the Stratix® 10 FPGA using embedded software for microprocessors. To illustrate the example, we use the Nios® II processor as the host to perform the Stratix® 10 FPGA configuration. This design is based on the Stratix® 10 SoC FPGA Development Kit. The Nios II processor that we use is programmed onto the MAX® 10 device on the board, which serves as the system controller for the development kit. The Nios II processor reads the Stratix® 10 FPGA configuration image from the flash and sends it to the Stratix® 10 FPGA via the Avalon® streaming (Avalon-ST) x16 interface. This software example is written for the Nios II processor; however, it should be portable to other microprocessor architectures by modifying the source codes. - 2020-02-10

Version

19.1.0

Product Type

Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition

Device Families > Stratix Families > Stratix 10

Resource Type

Developer Resources > Example Resources > Example Designs > System Example Designs

Source Name

Markdown