Arria® 10 FPGA – SoC Scalable Multispeed 10M – 10G Ethernet Design Example - This reference design describes a scalable multispeed 10M – 10G Ethernet design that demonstrates the Ethernet operations of the Low Latency Ethernet 10G MAC and Arria® 10 FPGA 1G/10G PHY Altera® FPGAs IP functions targeted on an Arria® 10 SoC FPGA development kit. It provides flexible test and demonstration platforms on which users can control, test, and monitor the Ethernet operations on the TX and RX datapaths. - 2017-03-14

Version

16.1.0