MAX® 10 FPGA – SDRAM RTL Design Example: Terasic DE10-Lite Board - This design example illustrates a test of the DE10-Lite Board's SDRAM written in Verilog HDL. The memory size of the SDRAM bank tested is 64 MB. - 2016-08-29
- Version
- 16.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Device Families > MAX Families > MAX 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown