MAX® 10 FPGA – SDRAM Nios® II Processor Design Example: Terasic DE10-Lite Board - This design example illustrates how to perform memory access in Qsys. It also shows how the SDRAM controller IP accesses SDRAM and how the Nios® II processor reads and writes the SDRAM for hardware verification. The SDRAM controller handles the complex aspects of accessing SDRAM, such as initializing the memory device, managing SDRAM banks, and keeping the devices refreshed at certain intervals. - 2016-08-26

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16.1.0