Arria® 10 FPGA – Scalable 10G Ethernet MAC + Native PHY with IEEE1588v2 Design Example - This reference design describes a scalable 10G Ethernet design with the IEEE 1588v2 feature that demonstrates the Ethernet operations of the Low Latency Ethernet 10G MAC Altera® FPGAs IP and Arria® 10 FPGA 1G/10G Native PHY functions as well as 10GBASE-R 1588 soft FIFO module targeted on an Arria® 10 FPGA SI development kit. It provides flexible test and demonstration platforms on which users can control, test, and monitor the Ethernet operations on the TX and RX datapaths. - 2017-03-14

Version

16.1.0