Cyclone® 10 LP FPGA – Synaptic Labs' Hyperbus Memory Controller IP Tutorial 003 - This reference design demonstrates how to build a clean-slate Nios® II processor system with HyperRAM using Synaptic Labs' Hyperbus Memory Controller (HBMC) intellectual property (IP) core on the Cyclone® 10 LP FPGA Evaluation Kit. Most HBMC customers using this board will want to start with the first tutorial. In this tutorial, you will build a Nios II processor-based embedded hardware system, download it to the development board, and run software programs written in 'C'. By the end of the session, you will have gained experience in how to build and run your own embedded system in an Cyclone® 10 LP device. This reference design is actively maintained by Synaptic Laboratories Ltd. Includes a free trial IP. - 2017-08-22
- Version
- 17.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown