Cyclone® V FPGA – Remote System Upgrade (RSU) Lab for the Terasic DE0-CV Kit - This design example demonstrates the ability of V series devices booting between two configuration images by initiating the ALTREMOTE_UPDATE IP, an Quartus® software built-in IP. The first chapter of the user guide will walk you through each of the steps to generate this design and eventually load the two configuration images (one factory image and one application image) on your FPGA. - 2016-06-30

Version

16.0.0