MAX® 10 FPGA – Power Management Controller Design Example - The power management controller design example allows you to allocate some applications in sleep mode during runtime. This reference design includes a simple finite state machine (FSM) to manage low-power state mode by powering down the I/O buffer and GCLK gating during sleep mode. This enables you to turn off portions of the design, thus reducing dynamic power consumption. You can re-enable your application with a fast wake-up time of less than 1 ms. You can modify the reference design based on your application. - 2016-06-02

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16.0.0