Cyclone® V FPGA – OpenLDI TX/RX Built-In Self Test (BIST) Design Example - This design example implements a simple built-in self test (BIST) of an Open LVDS Display Interface (Open LDI). The LVDS Serializer and Deserializer IP blocks are implemented with the ALTLVDS intellectual property (IP) core and are connected together with a simple external loopback HSMC card. A pseudorandom binary sequence (PRBS) pattern generator sends data to the serializer, which is looped back to the deserializer via the LVDS interface and sent to the PRBS checker block. - 2016-12-07

Version

16.0.0