Cyclone® 10 LP FPGA – Nios® II Processor Low Power Design Example - This low-power design example demonstrates how to use the Nios® II C-to-Hardware (C2H) Acceleration Compiler to help reduce dynamic power consumption in an FPGA-based embedded design. The example computes the Mandelbrot fractal pattern. This design example runs on the economical Cyclone® 10 LP FPGA Evaluation Kit. - 2017-12-18
- Version
- 17.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown