Cyclone® V FPGA – Nios® II Processor Compact Configuration for the Terasic DE0-CV Kit Design Example - This design uses a Nios® II processor and the Remote Update Altera® FPGAs IP core to reconfigure a Cyclone® V FPGA. The DE0-CV Kit has a configuration device EPCS64 which supports active serial (AS) configuration. Users can use a push button to switch between a factory image and an application image. - 2016-06-27

Version

16.0.0