MAX® 10 FPGA – Nios® II Processor-based Graphics Controller for LCD / TFT LCD Design Example - This design example demonstrates MAX® 10 FPGAs in a Nios® II processor-based graphics system. The design runs on Terasic's MAX® 10 FPGA NEEK Board and display, and has the following features: - Fits on an MAX® 10 FPGA 10M50 device - SDRAM program store and frame buffer - 3-layer display design supporting picture-in-picture, resizing, and alpha for all layers: Layer 0 - backdrop picture layer, RGB888; Layer 1 - backdrop text layer, RGB888 ; Layer 2 - video layer, RGB888. - 2017-01-02

Version

16.0.2