Cyclone® V FPGA – Nios® II Processor + Qsys "Hello World" Lab for the DE0-CV Kit - This step-by-step lab shows how to build a Nios® II processor Qsys-based system that includes GPIO, UART, and on-chip memory. This lab requires the DE0-CV Development Kit from Terasic. - 2016-06-08
- Version
- 16.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Device Families > Cyclone Families > Cyclone V
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown