MAX® 10 FPGA – Nios® II Processor + Qsys "Hello World" Lab - This step-by-step lab shows how to build a Nios® II processor Qsys-based system that includes GPIO, UART, and on-chip memory. This lab requires the MAX® 10 FPGA Development Kit. Appendix B in the lab manual describes how to combine the software image with the hardware .sof file. - 2018-04-03

Version

17.1.0