MAX® 10 FPGA – MAX® 10 FPGA DDR3 with Debug Feature Design Example - MAX® 10 FPGA DDR3 design with debug feature. Note that this design uses DDR3 memory and the pinout on the development kit changes based on the revision of your kit. See the MAX® 10 FPGA Development Kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits. - 2016-05-18

Version

16.0.0