MAX® 10 FPGA – Single-Port Triple Speed Ethernet and Onboard PHY Chip Design Example - This design example demonstrates the Triple Speed Ethernet IP solution for the MAX® 10 device family using the Triple Speed Ethernet Altera® FPGAs IP and Marvell 88E1111 PHY chip on the MAX® 10 FPGA Development Kit. It provides flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks. In this design, the Single-Port Triple-Speed Ethernet MAC connects to the onboard PHY chip through the Reduce Gigabit Media Independent Interface (RGMII). - 2018-04-10

Version

17.1.0