MAX® 10 FPGA – MAX® 10 FPGA Evaluation Kit Baseline Pinout - This design contains device pinouts only and can be used as a starting point for designing with your MAX® 10 FPGA Evaluation Kit. You can change the pin names as needed in the Verilog HDL code and the .qsf files (or with the Assignment Editor). Pin locations are locked down on the board. - 2015-12-15

Version

16.0.0