Arria® 10 FPGA – Low Latency Ethernet 10G MAC and XAUI PHY Reference Design - This design example demonstrates the Ethernet operations of the Arria® 10 FPGA Low Latency Ethernet 10G MAC and XAUI PHY IP with Dual XAUI to SFP+ HSMC board targeted on an Arria® 10 FPGA development kit. It provides flexible test and demonstration platforms on which users can control, test, and monitor the Ethernet operations using system loopback at various points. - 2016-05-16

Version

16.0.0