MAX® 10 FPGA – LCD Camera Display Design Example - This demonstration shows how to implement a camera display on the multi-touch LCD module in Qsys. The Video Image Processing (VIP) Suite Altera® FPGAs IP is used to display images on the LCD panel and a Nios® II processor is used to configure the I2C devices. There is a Camera IP from Terasic in Qsys, which translates the Bayer pattern from the camera to the RGB video stream format and feeds it to the VIP Suite Altera® FPGAs IP. The other IP developed by Terasic for auto-focus is used to find the optimized focus settings of the user-defined image areas. - 2016-05-17

Version

16.0.0