Agilex™ 7 FPGA - Triple-Speed Ethernet and On-Board PHY Chip Reference Design - The Altera® FPGAs Triple-Speed Ethernet and on-board PHY chip reference design demonstrates Ethernet operation between the Triple-Speed Ethernet IP core and onboard Marvell 88E1111 PHY chip through SGMII interface on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit. TCL scripts are included to allow users test the auto-negotiation feature, internal MAC loopback, internal PHY loopback and TX/RX interop with external tester at data rate of 10/100/1000 Mbps. Packet statistics report will be generated as the output result of the internal loopback test. - 2023-10-11

Version

23.3.0