Agilex™ 7 FPGA – Triple-Speed Ethernet and Onboard PHY Chip Reference Design - The Altera® FPGAs Triple-Speed Ethernet and on-board PHY chip reference design demonstrates the Ethernet operation between the Triple-Speed Ethernet IP core and on-board Marvell 88E1111 PHY chip through the SGMII interface on the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit. TCL scripts are included to allow users to test the auto-negotiation feature, internal MAC loopback, internal PHY loopback, and TX/RX interop with an external tester at a data rate of 10/100/1000 Mbps. A packet statistics report will be generated as the output result of the internal loopback test. - 2023-07-05

Version

23.1.0