Agilex™ 7 FPGA – Triple-Speed Ethernet and Onboard PHY Chip Reference Design - This reference design demonstrates the Ethernet operation between the Triple-Speed Ethernet IP core and onboard Marvell* 88E1111 PHY chip in the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit. - 2020-02-27
- Version
- 20.2.0
- Product Type
- Device Families > Agilex Families > Agilex 7 > F-Series
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown