Agilex™ 7 FPGA – Triple-Speed Ethernet and Onboard PHY Chip Reference Design - This reference design demonstrates the Ethernet operation between the Triple-Speed Ethernet IP core and onboard Marvell* 88E1111 PHY chip in the Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit. - 2020-02-27

Version

20.2.0