Arria® 10 FPGA – DisplayPort TX-Only Design Example - The Arria® 10 FPGA DisplayPort TX-only design demonstrates how the DisplayPort Altera® FPGAs IP source (TX) transmits 4Kp60 video output generated by the Test Pattern Generator II Altera® FPGAs IP core. This design uses the Bitec FMC daughter card to transmit the video output. The .par file contains 'Additional_Files.zip' and other design files. Unzip the 'Additional_Files.zip' file and run the 'build_sw.sh' script in the Nios® processor terminal to build the software prior to design compilation. - 2019-01-21

Version

18.1.0