Agilex™ 7 FPGA - I/O PLL Reconfiguration - This design example uses a Agilex™ 7 FPGA to demonstrate the implementation of the following three different I/O PLL reconfiguration option using the IOPLL Reconfig IP core. (1) .mif streaming (2) Advanced mode (3) Clock gating This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, In-System Sources & Probes Altera® FPGAs IP core and Reset Release Altera® FPGAs IP. - 2023-11-11

Version

23.3.0