Agilex™ 7 FPGA – I/O PLL Reconfiguration Design Example - This design example uses an Agilex™ 7 FPGA to demonstrate the implementation of the following three different I/O phase-locked loop (PLL) reconfiguration options using the IOPLL Reconfig Altera® FPGAs IP core: (1) .mif streaming (2) Advanced mode (3) Clock gating This design example consists of the IOPLL, IOPLL Reconfig, In-System Sources & Probes, and Reset Release Altera® FPGAs IP cores. - 2022-12-17
- Version
- 19.4.0
- Product Type
- Device Families > Agilex Families > Agilex 7 > F-Series
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown