Cyclone® 10 LP FPGA – HyperRAM MSGDMA Reference Design - This stand-alone tutorial describes a simple benchmarking reference design for Synaptic Laboratories Ltd's HyperBus Memory Controller (HBMC) intellectual property (IP) core targeted specifically for the Cyclone® 10 LP Evaluation Kit. This reference design is based on Altera®'s MSGDMA reference project. The tutorial describes the key aspects of a pre-configured .qsys reference project and the process of generating and compiling the project. The tutorial then describes how to compile the example Nios® II processor source code that controls Altera®'s MSGDMA and run the reference design on the development board. This reference design is actively maintained by Synaptic Laboratories Ltd. Includes a free trial IP. - 2017-08-04

Version

17.0.0