Arria® 10 FPGA – HDMI TX-Only VIP Suite Design Example - This reference design demonstrates the Altera® FPGAs High Definition Multimedia Interface (HDMI) 2.0 video connectivity IP core with a video processing pipeline based on IP cores from the Altera® FPGAs Video and Image Processing (VIP) Suite. This design is intended to show the interconnectivity between the HDMI IP core and the VIP Suite. This design demonstrates a simple configuration of a programmable oscillator via a Nios® II processor of a programmable oscillator on the Arria® 10 GX FPGA Development Kit to drive the TX IOPLL and fPLL reference clocks. - 2017-07-28

Version

17.0.0