Arria® 10 FPGA – HDMI 4Kp60 with Video and Image Processing Pipeline Reference Design - This reference design demonstrates the Altera® FPGAs High Definition Multimedia Interface (HDMI) 2.0 video connectivity IP core with a video processing pipeline based on IP cores from the Altera® FPGAs Video and Image Processing (VIP) Suite. This design is intended to show the interconnectivity between the HDMI IP core and the VIP Suite. Additionally, this design demonstrates the use of separate clocks for the RX and TX HDMI IP cores, allowing for differing RX and TX video resolutions. Finally, this design demonstrates the configuration of a programmable oscillator via a Nios® II processor on the Arria® 10 GX FPGA Development Kit to drive the TX IOPLL and fPLL reference clocks. - 2017-01-30

Version

16.1.2