Arria® 10 FPGA – FIR Filter for Complex Data and Coefficients Design Example - This design contains a complex-valued finite impulse response (FIR) filter that achieves a clock rate of 1 GHz on an Stratix® 10 FPGA. The associated white paper gives guidelines on how this can be achieved. - 2016-05-17
- Version
- 16.0.0
- Product Type
- Device Families > Arria Families > Arria 10
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown