Stratix® 10 FPGA – FIFO vs. FIFO2 Simulation Design Example - Stratix® 10 FPGAs offer two FIFO IP options – FIFO and FIFO2. FIFO is identical in other device families while FIFO2 is specifically designed with the Altera® HyperFlex™ architecture in mind, targeted for high-speed designs. Please refer to the Stratix® 10 Embedded Memory User Guide for the FIFO2 specification. Due to its pipelined structure, FIFO2 has a different latency compared to FIFO. This design shows the difference between FIFO and FIFO2 in the reset scheme and read/write operations. - No development kit required - Use the Quartus® Prime Software Version 18.0 and ModelSim* - The package contains a project that includes the source files: a top-level RTL, a testbench file, and a sim_top.tcl file to be sourced in ModelSim to run the simulation - 2018-12-10

Version

18.1.0