Cyclone® 10 GX FPGA – FFT to iFFT with Natural Input and Output Order Using Cosine Data Design Example - This design example demonstrates the implementation of fast Fourier transform (FFT) and inverse FFT (iFFT) functions with input and output orders configured in natural mode. Ideal cosine data is fed into the FFT block and the output from the FFT is connected to the iFFT for data verification. When both the FFT and iFFT are operating as expected, the cosine data will be recovered and observed at the iFFT output. This design example aims to assist users with the Cyclone® 10 GX FPGA FFT and iFFT intellectual property (IP) cores. In-System Sources and Probes (ISSP) is used to provide real-time control to the transceiver while the Signal Tap Logic Analyzer is used for status and data monitoring. - 2018-02-06

Version

17.1.0