Cyclone® 10 GX FPGA – Dynamic Reconfiguration with Transmitter PLL Switching Using a Nios® II Processor Design Example - This design example demonstrates the implementation of the Cyclone® 10 GX Native PHY Transmitter phase-locked loop (PLL) switching, channel reconfiguration with an embedded streamer or direct write method, as well as recalibration. - 2018-01-08

Version

17.1.0