Cyclone® 10 GX FPGA – Dynamic Reconfiguration with fPLL Switching with Direct Write Method Reference Design - This design example demonstrates the implementation of Cyclone® 10 GX FPGA Native PHY fractional phase-locked loop (fPLL) switching and channel reconfiguration using the direct-write method. The two fPLLs are used to support two different data rates which could not be achieved with a TX local divider. This design example aims to assist users with the Cyclone® 10 GX FPGA transceiver dynamic reconfiguration using the direct-write method. The simulation starts with the transceiver running at a 2 Gbps data rate and then reconfigured to 1.5 Gbps using fPLL switching and channel reconfiguration. After reconfiguration is completed, a channel recalibration is performed. Incremental data is sent from the TX and loopback to the RX for monitoring. In-System Sources and Probes (ISSP) is used to provide real-time control to the transceiver while the Signal Tap II Logic Analyzer is used for status and data monitoring. The dynamic reconfiguration and recalibration commands are performed through System Console. - 2017-12-28

Version

17.1.0