Cyclone® 10 GX FPGA – Dynamic Reconfiguration with ATX PLL Switching Reference Design - This design example demonstrates the implementation of Cyclone® 10 GX FPGA Native PHY auxiliary transmit (ATX) phase-locked loop (PLL) switching, channel reconfiguration with an embedded streamer, and recalibration. The two ATX PLLs are used to support two different data rates which could not be achieved with a TX local divider. This design example aims to assist users with the Cyclone® 10 GX FPGA transceiver dynamic reconfiguration. The design starts with the transceiver channel running at a 2 Gbps data rate and then reconfigured to 1.5 Gbps using ATX PLL switching and channel reconfiguration. After reconfiguration is complete, a channel recalibration followed by a reset is performed. Incremental data is sent from the TX and loopback to the RX for monitoring. In-System Sources and Probes (ISSP) is used to provide real-time control to the transceiver while the Signal Tap Logic Analyzer is used for status and data monitoring. The dynamic reconfiguration and recalibration commands are performed thro - 2017-12-14

Version

17.1.0