Cyclone® 10 LP FPGA – Dual-Core Nios® II Processor with Protected Memory Regions Design Example - This tutorial describes a simple design for Synaptic Laboratories Ltd's Interconnect intellectual property (IP) core for mapping a single memory region into private and shared memory regions for use with a multiprocessor system without a memory management unit (MMU) or memory protection unit (MPU). This reference design can be easily modified for other development boards and other Altera® FPGAs families. Includes a free trial IP. - 2017-12-15

Version

17.0.0