Agilex™ 7 FPGA - AN911: Achieving Timing Closure When Using Top I/O Sub Bank - This application note describes two methods to resolve these timing violations using the GPIO Altera® FPGAs IP. The analysis in this document focuses on the input data paths from the GPIO Altera® FPGAs IP to the FPGA core. There are 3 project revisions for this application note: 1. top - original design example with setup timing violation. 2. top_w1 - design example using negative edge clock latching solution. 3. top_w2 - design example using half-rate transfer mode solution. - 2023-10-19

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23.3.0