Agilex™ 7 FPGA – AN911: Achieving Timing Closure When Using Top I/O Sub Bank Design Example - This application note describes two methods to resolve these timing violations using the GPIO Altera® FPGAs IP. The analysis in this document focuses on the input datapaths from the GPIO Altera® FPGAs IP to the FPGA core. There are 3 project revisions for this application note: - top - original design example with setup timing violation. - top_w1 - design example using a negative edge clock latching solution. - top_w2 - design example using a half-rate transfer mode solution. - 2023-04-08

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23.1.0