MAX® 10 FPGA – DDR3 with Board Test System Console Design Example - The MAX® 10 FPGA Development Kit has one 64M x16 1Gb DDR3 SDRAM and one 128M x8 1Gb DDR3 SDRAM. The MAX® 10 FPGA provides full-speed support to a DDR3 300 MHz interface with an error correction code (ECC) feature. This design example is used to check out a x24 DDR3 300 MHz interface. Please download the MAX® 10 Development Kit installer and use the board test system (BTS) GUI to try it out. Note that this design uses DDR3 memory and the pinout on the development kit changes based on the revision of your kit. See the MAX® 10 Development Kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits. - 2016-04-29

Version

16.0.0