Arria® 10 FPGA – Data Word Alignment Calibration with Multiple PHY Lite for Parallel Interfaces IP Cores Design Example - This application note describes a design example demonstrating data alignment calibration using multiple PHY Lite for Parallel Interfaces IP cores. This design example emphasizes read latency configurations using a Nios® II processor. - 2017-03-07
- Version
- 16.1.0
- Product Type
- Device Families > Arria Families > Arria 10
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown