Cyclone® 10 GX FPGA – HDMI 4Kp60 with Video and Image Processing Pipeline Reference Design - This reference design demonstrates the Altera® FPGAs High Definition Multimedia Interface (HDMI) 2.0 video connectivity intellectual property (IP) core with a video processing pipeline based on IP cores from the Altera® FPGAs Video and Image Processing (VIP) Suite. This design is intended as a simple reference for interconnectivity between the HDMI IP core and the VIP Suite. Additionally, this design demonstrates the use of separate clocks for the RX and TX HDMI IP cores, allowing differing RX and TX video resolutions. - 2018-10-13

Version

18.0.1