Agilex™ 7 FPGA – Chip ID Reading Using Mailbox Client with Avalon® Streaming Interface Altera® FPGAs IP Design Example - This design example shows the chip ID reading functionality using the Avalon® Streaming Interface Altera® FPGAs IP with an Agilex™ 7 FPGA Development Kit. The chip ID reading functionality is implemented in Verilog and connects with the IP communicating with flash memory. - 2022-12-18

Version

22.4.0