Cyclone® 10 LP FPGA – Boot from EPCQ (Serial Flash) Design Example - This simple reference design demonstrates how to boot from the EPCQ memory on the Cyclone® 10 LP FPGA Evaluation Kit. It is based on Synaptic Laboratories Ltd's HyperBus Memory Controller (HBMC) intellectual property (IP) core and Altera®'s Serial Flash Controller IP core. The tutorial describes the key aspects of a pre-configured .qsys reference project and the process of generating and compiling the project. The tutorial then describes how to compile the example Nios® II processor source code, download the firmware into the EPCQ memory device, and run the reference design on the development board. This reference design is actively maintained by Synaptic Laboratories Ltd. This reference design can be easily modified for other development boards and other Altera® FPGAs families. Includes a free trial IP. - 2017-12-12

Version

17.1.0