MAX® 10 FPGA – Board Update Portal: Nios® II Processor, Flash, DDR3, Triple-Speed Ethernet, and UART Design Example - This design example is a web-server-based board update portal (BUP) design which contains a Nios® II processor, a Triple Speed Ethernet media access control (MAC) IP core, and a DDR3 IP core. It allows you to remotely update an FPGA system over Ethernet. For example, it can be used to update the firmware of an embedded FPGA system. The design is based on the Ethernet A port on the MAX® 10 FPGA Development Kit. Please download and install the board test system (BTS) installer for more details about the BUP design. Also, please see application note AN429: Remote Configuration Over Ethernet with the Nios II Processor (PDF) to learn more about remote updates. Note that this design uses DDR3 memory and the pinout on the development kit changes based on the revision of your kit. See the MAX® 10 Development Kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits. - 2016-04-28

Version

16.0.0