Arria® 10 FPGA – Board Update Portal Utilizing EPCQ Flash Memory Reference Design - This example is a web-based board update portal (BUP) which contains a Nios® II processor and a Triple-Speed Ethernet media access control (MAC) function. The design example implements basic remote configuration features in Nios II processor-based systems utilizing EPCQ flash memory for Arria® 10 GX FPGAs. The design can obtain an IP address from any DHCP server and serve a web page from the flash on the board to any host computer on the same network. Furthermore, this design supports a static IP address, where the developer must insert the required design manually before loading the design into EPCQ flash. The web page allows you to upload new design images for both user hardware and user software. Furthermore, you can trigger reconfiguration from factory image to user image through the web page. - 2016-12-21

Version

16.1.0