Cyclone® V FPGA – Board Update Portal Based on Nios® II Processors with EPCQ Design Example - This is a web-server-based board update portal (BUP) design that contains a Nios® II processor and a Triple-Speed Ethernet Media Access Control (MAC) Altera® FPGAs IP function. The design example implements basic remote configuration features in Nios II processor-based systems with EPCQ for Cyclone® V E FPGAs. The design can obtain an Internet Protocol address from any DHCP server and serve a web page from the flash on the board to any host computer on the same network. The web page allows you to upload new FPGA designs for both user hardware and user software. At the same time, you can also trigger reconfiguration from factory image to user image through the web page. - 2016-12-22

Version

16.0.0