Cyclone® 10 LP FPGA – Avalon® Verification IP Suite (Two Avalon Memory-Mapped Master and Slave Pair) Design Example - The Avalon® Verification IP Suite provides bus functional models (BFMs) to simulate the behavior of various Avalon interfaces. It also provides monitors to verify Avalon protocols. This suite facilitates the verification of intellectual property (IP) functions that include Avalon interfaces. - 2018-01-18

Version

17.0.0