Agilex™ 7 FPGA - AN901: Implementing Synchronized ADC Dual Link Design with JESD204C RX IP Core - This application note provides guidelines to scale up the single link in the JESD204C Altera® FPGAs IP core design example generated from the Quartus® Prime software to handle multipoint link system. A single link in JESD204C has one or more high speed transceiver lanes or channels. - 2023-10-08

Version

23.3.0